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a
Nonvolatile Memory, Dual 1024-Position Programmable Resistors ADN2850*
FUNCTIONAL BLOCK DIAGRAM
ADN2850
CS CLK SDI SDO PR WP RDY VDD VSS GND PWR ON PRESET EEMEM CONTROL EEMEM2 RDAC2 I1 CURRENT MONITOR I2 SERIAL INTERFACE EEMEM1 RDAC1 ADDR DECODE RDAC1 REGISTER W1 B1
FEATURES Dual, 1024-Position Resolution 25 k , 250 k Full-Scale Resistance Low Temperature Coefficient: 35 ppm/ C Nonvolatile Memory1 Preset Maintains Wiper Settings Permanent Memory Write-Protection Wiper Settings Read Back Actual Tolerance Stored in EEMEM1 Linear Increment/Decrement Log Taper Increment/Decrement SPI Compatible Serial Interface 3 V to 5 V Single Supply or 2.5 V Dual Supply 26 Bytes User Nonvolatile Memory for Constant Storage Current Monitoring Configurable Function 100-Year Typical Data Retention TA = 55 C APPLICATIONS SONET, SDH, ATM, Gigabit Ethernet, DWDM Laser Diode Driver Optical Supervisory Systems GENERAL DESCRIPTION
RDAC2 REGISTER W2 B2
26 BYTES USER EEMEM
V1
V2
RWB(D) - % of Full-Scale RWB
The ADN2850 provides dual-channel, digitally controlled programmable resistors2 with resolution of 1024 positions. These devices perform the same electronic adjustment function as a mechanical rheostat with enhanced resolution, solid-state reliability, and superior low temperature coefficient performance. The ADN2850's versatile programming via a standard serial interface allows 16 modes of operation and adjustment, including scratch pad programming, memory storing and retrieving, increment/decrement, log taper adjustment, wiper setting readback, and extra user defined EEMEM1. Another key feature of the ADN2850 is that the actual tolerance is stored in the EEMEM. The actual full-scale resistance can therefore be known, which is valuable for tolerance matching and calibration. In the scratch pad programming mode, a specific setting can be programmed directly to the RDAC2 register, which sets the resistance between terminals W and B. The RDAC register can also be loaded with a value previously stored in the EEMEM register. The value in the EEMEM can be changed or protected. When changes are made to the RDAC register, the value of the new setting can be saved into the EEMEM. Thereafter, such value will be transferred automatically to the RDAC register during system power ON, which is enabled by the internal preset strobe. EEMEM can also be retrieved through direct programming and external preset pin control.
*Patent pending
NOTES
1 2
100
75
50
25
0
0
256
512 CODE - Decimal
768
1023
Figure 1. RWB(D) vs. Decimal Code
The linear step increment and decrement commands enable the setting in the RDAC register to be moved UP or DOWN, one step at a time. For logarithmic changes in wiper setting, a left/right bit shift command adjusts the level in 6 dB steps. The ADN2850 is available in the 5 mm 5 mm 16-lead frame chip scale LFCSP and thin 16-lead TSSOP packages. All parts are guaranteed to operate over the extended industrial temperature range of -40C to +85C.
The term nonvolatile memory and EEMEM are used interchangeably. The term programmable resistor and RDAC are used interchangeably.
REV. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2002
ADN2850-SPECIFICATIONS
ELECTRICAL CHARACTERISTICS 25 k , 250 k
Parameter Symbol Conditions
VERSIONS
(VDD = 3 V to 5.5 V and -40 C < TA < +85 C, unless otherwise noted.)1
Min -2 -4 35 50 200 0.1 -30 VSS +30 VDD 11 80 0.01 2.4 0.8 2.1 0.6 2.0 0.5 4.9 0.4 2.25 5 2 100 Typ2 Max +2 +4 Unit LSB LSB ppm/C % % V pF pF A V V V V V V V V A pF V V A A mA mA A W %/% mA mA nV/Hz
DC CHARACTERISTICS RHEOSTAT MODE (Specifications apply to all RDACs) R-DNL RWB Resistor Differential Nonlinearity3 Resistor Integral Nonlinearity3 R-INL RWB Resistance Temperature Coefficient RWB/ T VDD = 5 V, IW = 100 A, Wiper Resistance RW Code = Half-scale VDD = 3 V, IW = 100 A, Code = Half-scale Channel Resistance Matching RWB/RWB Ch 1 and 2 RWB, Dx = 3FFH Nominal Resistor Tolerance RWB RESISTOR TERMINALS Terminal Voltage Range4 Capacitance5 Bx Capacitance5 Wx Common-Mode Leakage Current6 DIGITAL INPUTS AND OUTPUTS Input Logic High Input Logic Low Input Logic High Input Logic Low Input Logic High Input Logic Low Output Logic High (SDO, RDY) Output Logic Low Input Current Input Capacitance5 POWER SUPPLIES Single-Supply Power Range Dual-Supply Power Range Positive Supply Current Positive Supply Current Programming Mode Current Read Mode Current7 Negative Supply Current Power Dissipation8 Power Supply Sensitivity CURRENT MONITOR TERMINALS Current Sink at V19 Current Sink at V2 DYNAMIC CHARACTERISTICS5, 10 Resistor Noise Spectral Density Analog Crosstalk (CW1/CW2) VW, B CB CW ICM VIH VIL VIH VIL VIH VIL VOH VOL IIL CIL VDD VDD/VSS IDD IDD IDD(PG) IDD(XFR) ISS PDISS PSS I1 I2 eN_WB CT RWB_FS = 25 k/250 k, f = 1 kHz VB1 = VB2 = 0 V, Measured VW1 with VW2 = 100 mV p-p @ f = 100 kHz, Code 1 = Code 2 = 200H
f = 1 MHz, measured to GND, Code = Half-scale f = 1 MHz, measured to GND, Code = Half-scale VW = VB = VDD/2 With respect to GND, VDD = 5 V With respect to GND, VDD = 5 V With respect to GND, VDD = 3 V With respect to GND, VDD = 3 V With respect to GND, VDD = +2.5 V, VSS = -2.5 V With respect to GND, VDD = +2.5 V, VSS = -2.5 V RPULL-UP = 2.2 k to 5 V IOL = 1.6 mA, VLOGIC = 5 V VIN = 0 V or VDD
VSS = 0 V VIH = VDD or VIL = GND, TA = 25oC VIH = VDD or VIL = GND VIH = VDD or VIL = GND VIH = VDD or VIL = GND VIH = VDD or VIL = GND, VDD = +2.5 V, VSS = -2.5 V VIH = VDD or VIL = GND VDD = 5 V 10%
3.0 2.25 2 3.5 35 3 3.5 18 0.002 0.0001
5.5 2.75 4.5 6.0 9 6.0 50 0.01 10 10 20/64
0.3
-65
dB
-2-
REV. B
ADN2850
Parameter Symbol Conditions
5, 11
Min 20 10 1 10 5 5
Typ2
Max
Unit ns ns tCYC ns ns ns ns ns ns ns tCYC ns ms ms ns ns s
INTERFACE TIMING CHARACTERISTICS (apply to all parts) Clock Cycle Time (tCYC) t1 CS Setup Time t2 CLK Shutdown Time to CS Rise t3 Input Clock Pulsewidth t 4 , t5 Clock Level High or Low From Positive CLK Transition Data Setup Time t6 From Positive CLK Transition Data Hold Time t7 CS to SDO - SPI Line Acquire t8 CS to SDO - SPI Line Release t9 t10 RP = 2.2 k, CL < 20 pF CLK to SDO Propagation Delay12 CS High Pulsewidth13 t12 t13 CS High to CS High13 RDY Rise to CS Fall t14 CS Rise to RDY Fall Time t15 Applies to Command 2H, 3H, 9H Read/Store to Nonvolatile EEMEM14 t16 CS Rise to Clock Edge Setup t17 Preset Pulsewidth (Asynchronous) tPRW Not Shown in Timing Diagram PR Pulsed Low to Refresh Preset Response Time to Wiper Setting tPRESP Wiper Positions FLASH/EE MEMORY RELIABILITY Endurance15 Data Retention16
40 50 50 10 4 0 0.15 35 10 50 140 0.3
100 100
K Cycles Years
NOTES 1 Parts can be operated at 2.7 V single supply, except from 08C to -408C, where minimum 3 V is needed. 2 Typicals represent average readings at 258C and VDD = 5 V. 3 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. I W ~ 50 A for VDD = 2.7 V and IW ~ 400 A for VDD = 5 V. 4 Resistor terminals W and B have no limitations on polarity with respect to each other. 5 Guaranteed by design and not subject to production test. 6 Common-mode leakage current is a measure of the dc leakage from any terminal B and W to a common-mode bias level of V DD/2. 7 Transfer (XFR) mode current is not continuous. Current consumed while EEMEM locations are read and transferred to the RDAC register. See TPC 9. 8 PDISS is calculated from (I DD VDD) + (ISS VSS). 9 Applies to photodiode of optical receiver. 10 All dynamic characteristics use V DD = +2.5 V and V SS = -2.5 V. 11 See timing diagram for location of measured values. All input control voltages are specified with t R = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. Switching characteristics are measured using both V DD = 3 V and 5 V. 12 Propagation delay depends on value of V DD, RPULL_UP, and CL. See Applications section. 13 Valid for commands that do not activate the RDY pin. 14 RDY pin low only for commands 2, 3, 8, 9, 10, and PR hardware pulse: CMD_8 ~ 1 ms; CMD_9, 10 ~ 0.1 ms; CMD_2, 3 ~ 20 ms. Device operation at TA = -40C and VDD < 3 V extends the save time to 35 ms. 15 Endurance is qualified to 100,000 cycles as per JEDEC Std. 22 method A117 and measured at -40 C, +25C, and +85C; typical endurance at +25C is 700,000 cycles. 16 Retention lifetime equivalent at junction temperature (T J ) = 55C as per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6 V will derate with junction temperature. Specifications subject to change without notice. The ADN2850 contains 16,000 transistors. Die size: 93 mil 103 mil, 10,197 sq mil.
REV. B
-3-
ADN2850
TIMING DIAGRAMS
CS CPHA = 1
t12 t3 t2
CLK CPOL = 1
t13
t1 t5 t4 t10 t17 t11
LSB OUT
t8
SDO
t9
*
MSB
t7 t6
SDI MSB LSB
t14
RDY
t15 t16
*NOT DEFINED, BUT NORMALLY LSB OF CHARACTER PREVIOUSLY TRANSMITTED. THE CPOL = 1 MICROCONTROLLER COMMAND ALIGNS THE INCOMING DATA TO THE POSITIVE EDGE OF THE CLOCK.
Figure 2a. CPHA = 1 Timing Diagram
CS
CPHA = 0
t12 t1 t2
CLK CPOL = 0
t3 t5 t17
t13
t4
t8
t10 t11 t9
SDO
MSB OUT
LSB
*
t7 t6
SDI MSB IN LSB
t14
RDY
t15 t16
*NOT DEFINED, BUT NORMALLY MSB OF CHARACTER JUST RECEIVED. THE CPOL = 0 MICROCONTROLLER COMMAND ALIGNS THE INCOMING DATA TO THE POSITIVE EDGE OF THE CLOCK.
Figure 2b. CPHA = 0 Timing Diagram
-4-
REV. B
ADN2850
ABSOLUTE MAXIMUM RATINGS 1
(TA = 25C, unless otherwise noted.)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V, +7 V VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V, -7 V VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V VB, VW to GND . . . . . . . . . . . . . . . . VSS - 0.3 V, VDD + 0.3 V IB, I W Intermittent2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 mA Digital Inputs and Output Voltage to GND . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V, VDD + 0.3 V Operating Temperature Range3 . . . . . . . . . . . -40C to +85C Maximum Junction Temperature (TJ MAX) . . . . . . . . . 150C Storage Temperature . . . . . . . . . . . . . . . . . . -65C to +150C Lead Temperature, Soldering4 Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215 C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 C
Thermal Resistance Junction-to-Ambient JA, LFCSP-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35C/W TSSOP-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150C/W Thermal Resistance Junction-to-Case JC, TSSOP-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28C/W Package Power Dissipation = (TJ MAX - TA)/JA
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the B and W terminals at a given resistance. 3 Includes programming of nonvolatile memory. 4 Applicable to TSSOP-16 only. For LFCSP-16, please consult factory for details.
ORDERING GUIDE
Model ADN2850BCP25 ADN2850BCP25-RL7 ADN2850BCP250 ADN2850BCP250-RL7 ADN2850BRU25 ADN2850BRU25-RL7
RWB_FS (k ) 25 25 250 250 25 25
RDNL RINL (LSB) (LSB) 2 2 2 2 2 2 4 4 4 4 4 4
Temperature Package Range (C) Description -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 LFCSP-16 LFCSP-16 7" Reel LFCSP-16 LFCSP-16 7" Reel TSSOP-16 TSSOP-16 7" Reel
Package Option CP-16 CP-16 CP-16 CP-16 RU-16 RU-16
Ordering Quantity 96 1,000 96 1,000 96 1,000
Top Mark* BCP25 BCP25 BCP250 BCP250 2850B25 2850B25
*Line 1 contains product number, ADN2850, line 2 Top Mark branding contains differentiating detail by part type, line 3 contains lot number, line 4 contains product date code YYWW.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADN2850 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. B
-5-
ADN2850
PIN CONFIGURATIONS
CLK RDY
CLK 1
CS
16 RDY 15 CS 14 PR
SDI
SDI 2
12 PR
16 15 14 13
SDO 3 GND 4 VSS 5 V1 6 W1 7 B1 8
SDO 1 GND 2 VSS 3 V1 4
ADN2850BRU
TOP VIEW (Not To Scale)
ADN2850BCP
CHIP SCALE PACKAGE
5 6 7 8
11 WP 10 VDD 9
13 WP 12 VDD 11 V2 10 W2 9
V2
W1
W2
B1
B2
B2
ADN2850BCP PIN FUNCTION DESCRIPTIONS
ADN2850BRU PIN FUNCTION DESCRIPTIONS
Pin No. Mnemonic Description 1 SDO Serial Data Output Pin. Open-Drain output requires external pull-up resistor. CMD_9 and CMD_10 activate the SDO output. See Instruction Operation Truth Table (Table II). Other commands shift out the previously loaded SDI bit pattern delayed by 24 clock pulses. This allows daisy-chain operation of multiple packages. Ground Pin, logic ground reference Negative Supply. Connect to zero volts for single-supply applications. Log Output Voltage 1 generated from internal diode configured transistor Wiper terminal of RDAC1 ADDR (RDAC1) = 0H. B terminal of RDAC1 B terminal of RDAC2 Wiper terminal of RDAC2. ADDR (RDAC2) = 1H. Log Output Voltage 2 generated from internal diode configured transistor Positive Power Supply Pin Write Protect Pin. When active low, WP prevents any changes to the present register contents, except PR and CMD_1 and CMD_8 will refresh the RDAC register from EEMEM. Execute a NOP instruction before returning to WP high. Hardware Override Preset Pin. Refreshes the scratch pad register with current contents of the EEMEM register. Factory default loads midscale 51210 until EEMEM loaded with a new value by the user (PR is activated at the logic high transition). Serial Register chip select active low. Serial register operation takes place when CS returns to logic high. Ready. Active high open-drain output. Identifies completion of commands 2, 3, 8, 9, 10, and PR. Serial Input Register Clock Pin. Shifts in one bit at a time on positive clock edges. Serial Data Input Pin. Shifts in one bit at a time on positive clock CLK edges. MSB loaded first. -6-
Pin No. Mnemonic Description 1 2 CLK SDI Serial Input Register Clock Pin. Shifts in one bit at a time on positive clock edges. Serial Data Input Pin. Shifts in one bit at a time on positive clock CLK edges. MSB loaded first. Serial Data Output Pin. Open-drain out put requires external pull-up resistor. CMD_9 and CMD_10 activate the SDO output. See Instruction Operation Truth Table (Table II). Other commands shift out the previously loaded SDI bit pattern delayed by 24 clock pulses. This allows daisy-chain operation of multiple packages. Ground Pin, logic ground reference Negative Supply. Connect to zero volts for single-supply applications. Log Output Voltage 1 generated from internal diode configured transistor Wiper terminal of RDAC1. ADDR (RDAC1) = 0H. B terminal of RDAC1 B terminal of RDAC2 Wiper terminal of RDAC2. ADDR (RDAC2) = 1H. Log Output Voltage 2 generated from internal diode configured transistor Positive Power Supply Pin Write Protect Pin. When active low, WP prevents any changes to the present contents except PR and CMD_1 and CMD_8 will refresh the RDAC register from EEMEM. Execute a NOP instruction before returning to WP high. Hardware Override Preset Pin. Refreshes the scratch pad register with current contents of the EEMEM register. Factory default loads midscale 51210 until EEMEM loaded with a new value by the user (PR is activated at the logic high transition). Serial Register chip select active low. Serial register operation takes place when CS returns to logic high. Ready. Active high open-drain output. Identifies completion of commands 2, 3, 8, 9, 10, and PR. REV. B
3
SDO
2 3 4 5 6 7 8 9 10 11
GND VSS V1 W1 B1 B2 W2 V2 VDD WP
4 5 6 7 8 9 10 11 12 13
GND VSS V1 W1 B1 B2 W2 V2 VDD WP
12
PR
14
PR
13
CS
14 15 16
RDY CLK SDI
15
CS
16
RDY
ADN2850
Table I. 24-Bit Serial Data-Word
MSB
Instruction Byte 0 0 A3 0 0 A0 A2 A1 A0
Data Byte 1
Data Byte 0
LSB
RDAC C3 C2 C1 C0 EEMEM C3 C2 C1 C0
X X X X X X D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Command bits are C0 to C3. Address bits are A3-A0. Data bits D0 to D9 are applicable to RDAC wiper register whereas D0 to D15 are applicable to EEMEM Register. Command instruction codes are defined in Table II.
Table II. Instruction Operation Truth Table 1, 2, 3
Inst Number 0 1
Instruction Byte 0 Data Byte 1 Data Byte 0 Operation B23 * * * * * * * * * * * * * * * * B16 B15 * * * * * * B8 B7 * * * * * B0 C3 C2 C1 C0 A3 A2 A1 A0 X * * * * D9 D8 0 0 0 0 0 0 0 1 XXXX 0 0 0 A0 X****XX X****XX D7 * * * * * D0 X * * * * * * X NOP: Do nothing. See Table XI for Programming example. X * * * * * * X Retrieve contents of EEMEM(A0) to RDAC(A0) Register. This command leaves device in the Read Program power state. To return part to the idle state, perform NOP instruction 0. See Table XI. X * * * * * * X SAVE WIPER SETTING: Write contents of RDAC(A0) to EEMEM(A0). See Table X. D7 * * * * * D0 Write contents of Serial Register Data Bytes 0 and 1 (total 16-bit) to EEMEM(ADDR). See Table XIII. X * * * * * * X Decrement 6 dB: Right shift contents of RDAC(A0) Register, stops at all "Zeros." X * * * * * * X Decrement All 6 dB: Right shift contents of all RDAC Registers, stops at all "Zeros." X * * * * * * X Decrement contents of RDAC(A0) by "One," stops at all "Zeros." X * * * * * * X Decrement contents of all RDAC Registers by "One," stops at all "Zeros." X * * * * * * X RESET: Load all RDACs with their corresponding EEMEM previously saved values. X * * * * * * X Transfer contents of EEMEM (ADDR) to Serial Register Data Bytes 0 and 1, and previously stored data can be read out from the SDO pin. See Table XIV. X * * * * * * X Transfer contents of RDAC (A0) to Serial Register Data Bytes 0 and 1, and wiper setting can be read from the SDO pin. See Table XV. D7 * * * * * D0 Write contents of Serial Register Data Bytes 0 and 1 (total 11-bit) to RDAC(A0). See Table IX. X * * * * * * X Increment 6 dB: Left shift contents of RDAC(A0), stops at all "Ones." See Table XII. X * * * * * * X Increment All 6 dB: Left shift contents of all RDAC Registers, stops at all "Ones." X * * * * * * X Increment contents of RDAC(A0) by "One," stops at all "Ones." See Table X. X * * * * * * X Increment contents of all RDAC Registers by "One," stops at all "Ones."
2 34 45 55 65 75 8 9
0 0 0 0 0 0 1 1
0 0 1 1 1 1 0 0
1 1 0 0 1 1 0 0
0 1 0 1 0 1 0 1
0
0
0
A0
X****XX D15 * * * * D8 X****XX X****XX X****XX X****XX X****XX X****XX
A3 A2 A1 A0 0 0 0 A0
XXXX 0 0 0 A0
XXXX XXXX A3 A2 A1 A0
10
1
0
1
0
0
0
0
A0
X****XX
11 125 135 145 155
1 1 1 1 1
0 1 1 1 1
1 0 0 1 1
1 0 1 0 1
0 0
0 0
0 0
A0 A0
X * * * * D9 D8 X****XX X****XX X****XX X****XX
XXXX 0 0 0 A0
XXXX
NOTES 1 The SDO output shifts out the last 24 bits of data clocked into the serial register for daisy-chain operation. Exception: for any instruction following Instruction 9 or 10, the selected internal register data will be present in data byte 0 and 1. The instructions following 9 and 10 must also be a full 24-bit data-word to completely clock out the contents of the serial register. 2 The RDAC register is a volatile scratch pad register that is refreshed at power ON from the corresponding nonvolatile EEMEM register. 3 Execution of the above operations takes place when the CS strobe returns to logic high. 4 Instruction 3 writes 2 data bytes (total 16-bit) to EEMEM. But in the cases of addresses 0 and 1, only the last 10 bits are valid for wiper position setting. 5 The increment, decrement, and shift commands ignore the contents of the shift register data bytes 0 and 1.
REV. B
-7-
ADN2850
OPERATIONAL OVERVIEW
The ADN2850 programmable resistor is designed to operate as a true variable resistor. The resistor wiper position is determined by the RDAC register contents. The RDAC register acts as a scratch pad register which allows unlimited changes of resistance settings. The scratch pad register can be programmed with any position setting using the standard SPI serial interface by loading the 24-bit data-word. The format of the data-word is that the first 4 bits are instructions, the following 4 bits are addresses, and the last 16 bits are data. Once a specific value is set, this value can be saved into a corresponding EEMEM register. During subsequent power-ups, the wiper setting will automatically be loaded at that value. Saving data to the EEMEM takes about 25 ms and consumes approximately 20 mA. During this time the shift register is locked, preventing any changes from taking place. The RDY pin indicates the completion of this EEMEM saving process. There are also 13 two-bytes addresses, of user defined data that can be stored in EEMEM.
OPERATION DETAIL
Table III. Set and Save RDAC with Independent Data to EEMEM Registers
SDI B00100H 20xxxxH B10200H 21xxxxH
SDO XXXXXXH B00100H 20xxxxH B10200H
Action Loads data 100H into RDAC1 register, Wiper W1 moves to 1/4 full-scale position. Saves copy of RDAC1 register content into corresponding EEMEM1 register. Loads 200H data into RDAC2 register, Wiper W2 moves to 1/2 full-scale position. Saves copy of RDAC2 register contents into corresponding EEMEM2 register.
There are 16 instructions that facilitate users' programming needs. Referring to Table II, the instructions are: 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. Do Nothing Restore EEMEM setting to RDAC Save RDAC setting to EEMEM Save user data or RDAC setting to EEMEM Decrement 6 dB Decrement all 6 dB Decrement one step Decrement all one step Reset all EEMEM settings to RDAC Read EEMEM to SDO Read Wiper Setting to SDO Write data to RDAC Increment 6 dB Increment all 6 dB Increment one step Increment all one step
At system power ON, the scratch pad register is automatically refreshed with the value previously saved in the corresponding EEMEM register. The factory preset EEMEM value is midscale. During operations, the scratch pad register can also be refreshed with the current contents of the EEMEM registers in three different ways. First, executing instruction 1 retrieves the corresponding EEMEM value. Second, executing instruction 8 resets the EEMEM values of both channels. Finally, pulsing the PR pin also refreshes both EEMEM settings. Operating the hardware control PR function, however, requires a complete pulse signal. When PR goes low, the internal logic sets the wiper at midscale. The EEMEM value will not be loaded until PR returns to high.
EEMEM Protection
The write-protect (WP) disables any changes of the scratch pad register contents regardless of the software commands, except that the EEMEM setting can be refreshed and can overwrite the WP by using commands 1, 8, and PR pulse. To disable WP, it is recommended to execute a NOP command before returning WP to logic high.
Linear Increment and Decrement Commands
Tables VIII to XIV provide a few programming examples by using some of these instructions.
Scratch Pad and EEMEM Programming
The basic mode of setting the programmable resistor wiper position (programming the scratch pad register) is done by loading the serial data input register with the instruction 11, the corresponding address, and the data. Since the scratch pad register is a standard logic register, there is no restriction on the number of changes allowed. When the desired wiper position is determined, the user can load the serial data input register with the instruction 2, which stores the setting into the corresponding EEMEM register. The EEMEM value can be changed at any time or permanently protected by activating the WP command. Table III provides a programming example listing the sequence of serial data input (SDI) words and the corresponding serial data output (SDO) in hexadecimal format.
The increment and decrement commands (14, 15, 6, 7) are useful for linear step adjustment applications. These commands simplify microcontroller software coding by allowing the controller to just send an increment or decrement command to the device. The adjustment can be individually or gang controlled. For increment command, executing instruction 14 will automatically move the wiper to the next resistance segment position. The master increment instruction 15 will move all resistor wipers up by one position.
Logarithmic Taper Mode Adjustment ( 6 dB/step)
There are four programming instructions which provide the logarithmic taper increment and decrement wiper position control by either individual or gang control. 6 dB increment is activated by instructions 12 and 13 and 6 dB decrement is activated by instructions 4 and 5. For example, starting at zero scale, executing 11 times the increment instruction 12 will move the wiper in 6 dB per step from the 0% of the full-scale RWB to the full-scale RWB. The 6 dB increment instruction doubles the value of the RDAC register contents each time the command is executed. When the wiper position is near the maximum setting, the last 6 dB increment instruction will cause the wiper to go to the full-scale 1023-code position. Further 6 dB per increment instruction will no longer change the wiper position beyond its full-scale, Table IV. 6 dB step increment and decrement are achieved by shifting the bit internally to the left and right, respectively. The following information explains the nonideal 6 dB step adjustment at certain -8- REV. B
ADN2850
conditions. Table IV illustrates the operation of the shifting function on the individual RDAC register data bits. Each line going down the table represents a successive shift operation. Note that the left shift 12 and 13 commands were modified such that if the data in the RDAC register is equal to zero, and the data is left shifted, the RDAC register is then set to code 1. Similarly, if the data in the RDAC register is greater than or equal to midscale, and the data is left shifted, then the data in the RDAC register is automatically set to full scale. This makes the left shift function as ideal a logarithmic adjustment as possible. The right shift 4 and 5 commands will be ideal only if the LSB is zero (i.e., ideal logarithmic--no error). If the LSB is a one, then the right shift function generates a linear half LSB error, which translates to a number of bits-dependent logarithmic error as shown in Figure 3. The plot shows the error of the odd numbers of bits for ADN2850.
Table IV. Detail Left and Right Shift Functions for 6 dB Step Increment and Decrement Using Additional Internal Nonvolatile EEMEM
The ADN2850 contains additional internal user storage registers (EEMEM) for saving constants and other 16-bit data. Table V provides an address map of the internal storage registers shown in the functional block diagram as EEMEM1, EEMEM2, and and 26 bytes (13 addresses 2 bytes each) of USER EEMEM.
Table V. EEMEM Address Map
EEMEM Number 1 2 3 4 : 15 16
Address 0000 0001 0010 0011 : 1110 1111
EEMEM Content For RDAC11, 2 RDAC2 USER13 USER2 : USER13 % Tolerance4
Left Shift 00 0000 0000 00 0000 0001 00 0000 0010 00 0000 0100 00 0000 1000 00 0001 0000 00 0010 0000 00 0100 0000 00 1000 0000 01 0000 0000 10 0000 0000 11 1111 1111 11 1111 1111
Right Shift 11 1111 1111 01 1111 1111 00 1111 1111 00 0111 1111 00 0011 1111 00 0001 1111 00 0000 1111 00 0000 0111 00 0000 0011 00 0000 0001 00 0000 0000 00 0000 0000 00 0000 0000
NOTES 1 RDAC data stored in EEMEM locations are transferred to their corresponding RDAC REGISTER at power-on, or when instructions 1, 8, and PR are executed. 2 Execution of instruction 1 leaves the device in the read mode power consumption state. After the last instruction 1 is executed, the user should perform a NOP, instruction 0 to return the device to the low power idling state. 3 USER are internal nonvolatile EEMEM registers available to store and retrieve constants and other 16-bit information using instructions 3 and 9 respectively. 4 Read only.
Left Shift 6 dB/step
Right Shift -6 dB/step
Calculating Actual Full-Scale Resistance
The actual tolerance of the rated full-scale resistance RWB1 is stored in EEMEM register 15 during factory testing. The actual full-scale resistance can therefore be calculated, which will be valuable for tolerance matching or calibration. Notice this value is read only, and the full-scale resistance of RWB2_FS matches RWB1_FS, of typically 0.1%. The tolerance in % is stored in the last 16 bits of data in EEMEM register 15. The format is sign magnitude binary format with the MSB designates for sign (0 = positive and 1 = negative), the next 7 MSB designate for the integer number, and the 8 LSB designate for the decimal number. See Table VI.
Table VI. Tolerance in % from Rated Full-Scale Resistance
Bit D15 D14 D13 D12 D11 D10 D9 D8 sign mag sign 26 25 24 23 22 21 20 D7 D6 D5 D4 D3 D2 D1 D0 * 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 8 Bits for Decimal Number
Actual conformance to a logarithmic curve between the data contents in the RDAC register and the wiper position for each right shift 4 and 5 command execution contains an error only for odd numbers of bits. Even numbers of bits are ideal. The graph in Figure 3 shows plots of Log_Error [i.e., 20 log10 (error/code)] ADN2850. For example, code 3 Log_Error = 20 log10 (0.5/3) = -15.56 dB, which is the worst case. The plot of Log_Error is more significant at the lower codes.
0
-20
-40
For example, if RWB_FS_RATED = 250 k and the data is 0001 1100 0000 1111, RWB_FS_ACTUAL can be calculated as follows: MSB: 0 = Positive Next 7 MSB: 001 1100 = 28 8 LSB: 0000 1111 = 15 2-8 = 0.06 % Tolerance = +28.06% Thus, RWB_FS_ACTUAL = 320.15 k
{
Sign
{ {
7 Bits for Integer Number Decimal Point
{
dB
-60
-80
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8 103
0.9
1.0
1.1
CODE - From 1 to 1023 by 2.0
Figure 3. Plot of Log_Error Conformance for Odd Numbers of Bits Only (Even Numbers of Bits Are Ideal)
REV. B
-9-
ADN2850
Daisy-Chain Operation
PR VALID COMMAND COUNTER WP
The serial data output pin (SDO) serves two purposes. It can be used to read out the contents of the wiper settings or EEMEM values using instructions 10 and 9 respectively. If these instructions are not used, SDO can be used for daisy-chaining multiple devices in simultaneous operations (see Figure 4). The SDO pin contains an open-drain N-Ch FET and requires a pull-up resistor if SDO function is used. Users need to tie the SDO pin of one package to the SDI pin of the next package. Users may need to increase the clock period because the pull-up resistor and the capacitive loading at the SDO-SDI interface may induce time delay to the subsequent devices (see Figure 4). If two ADN2850s are daisy-chained, a total 48 bits of data is required. The first 24 bits (formatted 4-bit instruction, 4-bit address, and 16-bit data) go to U2 and the second 24 bits with the same format go to U1. The CS should be kept low until all 48 bits are clocked into their respective serial registers. The CS is then pulled high to complete the operation.
VDD
COMMAND PROCESSOR AND ADDRESS DECODE
5V
RPULLUP CLK SERIAL REGISTER SDO CS SDI GND
ADN2850
Figure 5. Equivalent Digital Input-Output Logic
VDD
LOGIC PINS
INPUTS 300
ADN2850
U1 MOSI C SCLK SS SDI SDO
RP 2.2k
ADN2850
U2 SDI SDO
GND
CS CLK CS CLK
Figure 6a. Equivalent ESD Digital Input Protection
VDD
Figure 4. Daisy-Chain Configuration
DIGITAL INPUT/OUTPUT CONFIGURATION
INPUT 300 WP
All digital inputs are ESD protected. Digital inputs are high impedance and can be driven directly from most digital sources. Active at logic low, PR and WP should be biased to VDD if they are not used. There are no internal pull-up resistors present on any digital input pins. To avoid floating digital pins that may cause false triggering in a noisy environment, pull-up resistors should be added to these pins. However, this only applies to the case where the device will be detached from the driving source once it is programmed. The SDO and RDY pins are open-drain digital outputs. Similarly, pull-up resistors are needed if these functions are used. To optimize the speed and power trade-off, use 2.2 k pull-up resistors. The equivalent serial data input and output logic is shown in Figure 5. The open-drain output SDO is disabled whenever chip select CS is logic high. ESD protection of the digital inputs is shown in Figures 6a and 6b.
GND
Figure 6b. Equivalent WP Input Protection
SERIAL DATA INTERFACE
The ADN2850 contains a 4-wire, SPI compatible, digital interface (SDI, SDO, CS, and CLK). The 24-bit serial word must be loaded with MSB first, and the format of the word is shown in Table I. The Command Bits (C0 to C3) control the operation of the programmable resistor according to the instruction shown in Table II. A0 to A3 are assigned for address bits. A0 is used to address RDAC1 or RDAC2. Addresses 2 to 14 are accessible by users. Address 15 is reserved for the factory. Table V provides an address map of the EEMEM locations. The data bits (D0 to D9) are the values that are loaded into the RDAC registers at instruction 11. The data bits (D0 to D15) are the values that are loaded into the EEMEM registers at instruction 3. The last instruction prior to a period of no programming activity should be applied with the No Operation (NOP), instruction 0. It is recommended to do so to ensure minimum power consumption in the internal logic circuitry The SPI interface can be used in two slave modes, CPHA = 1, CPOL = 1 and CPHA = 0, CPOL = 0. CPHA and CPOL refer to the control bits that dictate SPI timing in these microconverters and microprocessors: ADuC812/ADuC824, M68HC11, and MC68HC16R1/916R1. -10- REV. B
ADN2850
TERMINAL VOLTAGE OPERATING RANGE
ADN2850
VDD C3 10 F C4 10 F + + C1 0.1 F C2 0.1 F VDD
The ADN2850 positive VDD and negative VSS power supply defines the boundary conditions for proper two-terminal programmable resistance operation. Supply signals present on terminals W and B that exceed VDD or VSS will be clamped by the internal forward biased diodes (see Figure 7).
VDD
VSS
VSS GND
Figure 8. Power Supply Bypassing
RDAC STRUCTURE
W B
VSS
Figure 7. Maximum Terminal Voltages Set by VDD and VSS
The ground pin of the ADN2850 device is primarily used as a digital ground reference that needs to be tied to the PCB's common ground. The digital input control signals to the ADN2850 must be referenced to the device ground pin (GND), and satisfy the logic level defined in the Specifications table of this data sheet. An internal level shift circuit ensures that the common-mode voltage range of the two terminals extends from VSS to VDD regardless of the digital input level. In addition, there is no polarity constraint on voltage across terminals W and B. The magnitude of |VWB| is bounded by VDD - VSS.
Power-Up Sequence
The patent-pending RDAC contains a string of equal resistor segments, with an array of analog switches, that act as the wiper connection. The number of positions is the resolution of the device. The ADN2850 has 1024 connection points, allowing it to provide better than 0.1% setability resolution. Figure 9 shows an equivalent structure of the connections between the two terminals that make up one channel of the RDAC. The SWB will always be ON, while one of the switches SW(0) to SW(2N - 1) will be ON one at a time depending on the resistance position decoded from the data bits. Since the switch is not ideal, there is a 50 wiper resistance, RW. Wiper resistance is a function of supply voltage and temperature. The lower the supply voltage or the higher the temperature, the higher the resulting wiper resistance. Users should be aware of the wiper resistance dynamics if accurate prediction of the output resistance is needed.
SW(2N-1)
RS RDAC WIPER REGISTER AND DECODER
W SW(2N- 2)
Since diodes limit the voltage compliance at terminals B and W (see Figure 7) it is important to power VDD/VSS first before applying any voltage to terminals B and W. Otherwise, the diode will be forward biased such that VDD/VSS will be powered unintentionally. For example, applying 5 V across VDD will cause the VDD terminal to exhibit 4.3 V. Although it is not destructive to the device, it may affect the rest of the user's system. As a result, the ideal power-up sequence is in the following order: GND, VDD, VSS, Digital Inputs, and VB/W. The order of powering VB, VW, and Digital Inputs is not important as long as they are powered after VDD/VSS. Regardless of the power-up sequence and the ramp rates of the power supplies, once VDD/VSS are powered, the power-on reset remains effective, which retrieves EEMEM saved values to the RDAC registers (see TPC 7).
Layout and Power Supply Bypassing
RS
SW(1)
RS RS = RWB / 2N DIGITAL CIRCUITRY OMITTED FOR CLARITY
SW(0)
SWB B
Figure 9. Equivalent RDAC Structure
Table VII. Nominal Individual Segment Resistor Values
Device Resolution 1024-Step
25 k 24.4
250 k 244
It is a good practice to employ compact, minimum-lead length layout design. The leads to the input should be as direct as possible with a minimum of conductor length. Ground paths should have low resistance and low inductance. To minimize the digital ground bounce, the digital signal ground reference can be joined remotely to the analog ground terminal of the ADN2850. Similarly, it is also a good practice to bypass the power supplies with quality capacitors for optimum stability. Supply leads to the device should be bypassed with 0.01 F to 0.1 F disc or chip ceramics capacitors. Low ESR 1 F to 10 F tantalum or electrolytic capacitors should also be applied at the supplies to minimize any transient disturbance (see Figure 8).
CALCULATING THE PROGRAMMABLE RESISTANCE
The nominal full-scale resistance of the RDAC between terminals W and B, RWB_FS, is available with 25 k and 250 k with 1024 positions (10-bit resolution). The final digits of the part number determine the nominal resistance value, e.g., 25 k = 25 and 250 k = 250. The 10-bit data-word in the RDAC latch is decoded to select one of the 1024 possible settings. The following discussion describes the calculation of resistance RWB(D) at different codes of a 25 k part. The wiper's first connection starts at the B terminal for data 000H. RWB(0) is 50 because of the wiper resistance and it is independent of the full-scale resistance. The second connection is the first tap point where RWB(1) becomes 24.4 + 50 = 74.4
REV. B
-11-
ADN2850
for data 001H. The third connection is the next tap point representing RWB(2) = 48.8 + 50 = 98.8 for data 002H and so on. Each LSB data value increase moves the wiper up the resistor ladder until the last tap point is reached at RWB(1023) = 25026 . See Figure 9 for a simplified diagram of the equivalent RDAC circuit.
25 RWB_FS = 25k 20
The general equation that determines the programmed output resistance between Wx and Bx is: D RWB ( D ) = x RWB _ FS + RW (1) 1024 where D is the decimal equivalent of the data contained in the RDAC register, RWB_FS is the full-scale resistance between terminals W and B, and RW is the wiper resistance. For example, the following output resistance values will be set for the following RDAC latch codes with VDD = 5 V (applies to RWB_FS = 25 k programmable resistors):
Table VIII. RWB at Selected Codes (RWB_FS = 25 k )
RWB (D) - k
15
10
D (DEC) 1023 512 1 0
0 256 512 CODE - Decimal 768 1023
RWB(D) () 25026 12550 74.4 50
Output State Full-Scale Mid Scale 1 LSB Zero-Scale (Wiper contact resistance)
5
0
Figure 10. RWB(D) vs. Code
Note that in the zero-scale condition a finite wiper resistance of 50 is present. In this state, care should be taken to limit the current flow between W and B to no more than 20 mA to avoid degradation or possible destruction of the internal switches. Channel-to-channel RWB matching is well within 1% at fullscale. The change in RWB with temperature has a 35 ppm/C temperature coefficient.
-12-
REV. B
Typical Performance Characteristics-ADN2850
1.0 0.8 0.6
R-INL ERROR - LSB
30
+25 C -40 C +85 C
36 34 32
0.4 0.2 0 -0.2
OHMS
28 26 24 22 20
-0.4 -0.6
18
0
200
400
600
800
1000
16
0
200
400
600 CODE
800
1000
1200
DIGITAL CODE
TPC 1. R-INL vs. Code, TA = 85 C Overlay, RAB = 25 k
40 C,
25 C,
TPC 4. Wiper On-Resistance vs. Code
0.4
4
0.2
R-DNL ERROR - LSB
3 IDD @ V DD/V SS = 5V/0V
CURRENT - A
0
2
-0.2
1 ISS @ V DD/V SS = 5V/0V
-0.4
0
-0.6
IDD @ V DD/V SS = 2.7V/0V ISS @ V DD/V SS = 2.7V/0V
-0.8
0
200
400
600
800
1000
-1 -40
-20
0
20
40
60
80
100
DIGITAL CODE
TEMPERATURE - C
TPC 2. R-DNL vs. Code, TA = 85 C Overlay, RAB = 25 k
40 C,
25 C,
TPC 5. IDD vs. Temperature, RAB = 25 k
120
RHEOSTAT MODE TEMPCO - ppm/ C
0.25
100 80 60
VDD /VSS = 5.0V/0V TA = 25 C
0.20
VDD/V SS = 5V/0V RAR = 25k
FULL SCALE MIDSCALE
IDD - mA
40 20 0 -20 25k -40 250k -60 -80 0 128 256 384 512 640 768 896 1023 CODE - Decimal VERSION VERSION
0.15 ZERO SCALE
0.10
0.05
0 0.0E+00
2.0E+06
4.0E+06
6.0E+06
8.0E+06
1.0E+07
1.2E+07
FREQUENCY - Hz
TPC 3. RWB /T Rheostat Mode Tempco
TPC 6. IDD vs. Clock Frequency, RAB = 25 k
REV. B
-13-
ADN2850
NORMALIZED RESISTANCE
IW = I A TA = 25 C 0.5V/DIV RWB(D)
THEORETICAL - IWB_MAX - mA
100 TA = 25 C
10
MIDSCALE
EXPECTED VALUE
1
RWB_FS = 25k
50 S/DIV
0.1 RWB_FS = 250k
TPC 7. Memory Restore During Power-On Reset
0.01 0 128 256 384 512
640
768
896
1024
CODE - Decimal
5V/DIV
CS
TPC 10. IWB_MAX vs. Code
TEST CIRCUITS
5V/DIV
CLK
Test Circuits 1 to 3 show some of the test conditions used in the Specifications table.
NC DUT A W B VMS IW
5V/DIV
VSDI
IDD 20mA/DIV
4ms/DIV
TPC 8. IDD vs. Time (Save) Program Mode
NC = NO CONNECT
5V/DIV
CS
Test Circuit 1. Resistor Position Nonlinearity Error (Rheostat Operation; R-INL, R-DNL)
5V/DIV
CLK
DUT
5V/DIV
RSW =
0.1V ISW +
SDI
W B ISW
CODE = 00H 0.1V
_ VSS TO V DD
IDD 2mA/DIV
4ms/DIV
SUPPLY CURRENT RETURNS TO MINIMUM POWER CONSUMPTION IF INSTRUCTION 0 (NOP) IS EXECUTED IMMEDIATELY AFTER INSTRUCTION 1 (READ EEMEM)
Test Circuit 2. Incremental ON Resistance
NC VDD DUT VSS GND A W B VCM ICM
TPC 9. IDD vs. Time (Read) Program Mode
NC NC = NO CONNECT
Test Circuit 3. Common-Mode Leakage Current
-14-
REV. B
ADN2850
PROGRAMMING EXAMPLES Table XII. Using Left Shift by One to Increment 6 dB Steps
The following programming examples illustrate the typical sequence of events for various features of the ADN2850. Users should refer to Table II for the instructions and data-word format. The instruction numbers, addresses, and data appearing at SDI and SDO pins are displayed in hexadecimal format in the following examples.
Table IX. Scratch Pad Programming
SDI
SDO
Action
C0XXXXH XXXXXXH Moves wiper 1 to double the present data contained in RDAC1 register. C1XXXXH C0XXXXH Moves wiper 2 to double the present data contained in RDAC2 register.
Table XIII. Storing Additional User Data in EEMEM
SDI B00100H B10200H
SDO XXXXXXH B00100H
Action Loads data 100H into RDAC1 register, Wiper W1 moves to 1/4 full-scale position. Loads data 200H into RDAC2 register, Wiper 2 moves to 1/2 full-scale position. SDI
SDO
Action
32AAAAH
335555H
Table X. Incrementing RDAC Followed by Storing the Wiper Setting to EEMEM
SDI B00100H
SDO
Action
XXXXXXH Stores data AAAAH into spare EEMEM location USER1. (Allowable to address in 13 locations with maximum 16 bits of data). 32AAAAH Stores data 5555H into spare EEMEM location USER2. (Allowable to address in 13 locations with maximum 16 bits of data).
XXXXXXH Loads data 100H into RDAC1 register, Wiper W1 moves to 1/4 full-scale position. E0XXXXH B00100H Increments RDAC1 register by one to 101H. E0XXXXH E0XXXXH Increments RDAC1 register by one to 102H. Repeat the increment command - (E0XXXXH) until desired wiper position is reached 20XXXXH XXXXXXH Saves RDAC1 data into EEMEM1 Optionally tie WP to GND to protect EEMEM values
Table XI. Restoring EEMEM Values to RDAC Registers
Table XIV. Reading Back Data From Various Memory Locations
SDI
SDO
Action
92XXXXH XXXXXXH Prepares data read from USER1 location. 00XXXXH 92AAAAH NOP instruction 0 sends 24-bit word out of SDO where the last 16 bits contain the contents of USER1 location. NOP command ensures device returns to idle power dissipation state.
Table XV. Reading Back Wiper Setting
EEMEM values for RDACs can be restored by: Power-On, Strobing PR pin or Programming shown below. SDI SDO Action
SDI
SDO
Action
10XXXXH XXXXXXH Restores EEMEM1 value to RDAC1 register. NOP. Recommended step to minimize 00XXXXH 100100H power consumption. 8XXXXXH 00XXXXH Reset EEMEM1 and EEMEM2 values to RDAC1 and RDAC2 registers respectively.
B00200H XXXXXXH Sets RDAC1 to midscale. Doubles RDAC1 from midscale to C0XXXXH B00200H full-scale. A0XXXXH C0XXXXH Prepares reading wiper setting from RDAC1 register. Readback full-scale value from RDAC1 XXXXXXH A003FFH register. Analog Devices offers a user-friendly ADN2850EVAL evaluation kit that can be controlled by a personal computer through the printer port. The driving program is self-contained, so no programming languages or skills are needed.
REV. B
-15-
ADN2850
APPLICATIONS Optical Transmitter Calibration with ADN2841
VCC VCC
Together with the multirate 2.7 Gbps Laser Diode Driver ADN2841, the ADN2850 forms an optical supervisory system where the dual programmable resistors are used to set the laser average optical power and extinction ratio (see Figure 11). The ADN2850 is particularly ideal for the optical parameter settings because of its high resolution, compact footprint, and superior temperature coefficient characteristics. The ADN2841 is a 2.7 Gbps laser diode driver that uses a unique control algorithm to manage both the laser average power and extinction ratio after the laser initial factory calibration. It stabilizes the laser data transmission by continuously monitoring its optical power, and correcting the variations caused by temperature and the laser degradation over time. In the ADN2841, the IMPD monitors the laser diode current. Through its dual-loop power and extinction ratio control, calibrated by the ADN2850, the internal driver controls the bias current IBIAS and consequently the average power. It also regulates the modulation current IMODP by changing the modulation current linearly with slope efficiency. Any changes in the laser threshold current or slope efficiency are therefore compensated. As a result, this optical supervisory system minimizes the laser characterization efforts and enables designers to apply comparable lasers from multiple sources.
Incoming Optical Power Monitoring
ADN2850
RDAC1 CS CLK SDI EEMEM B2 ERSET IDTONE DINQ DIN CONTROL RDAC2 W2 W1
IMPD
ADN2841
EEMEM
B1
PSET
IMODP IBIAS
DIN DINQ IDTONE
Figure 11. Optical Supervisory System
Knowing IC1 = a1 IPD, IC2 = a2 IREF, and Q1- Q2 are matched, therefore a and IS are matched. Combining Equations 2 and 3 theoretically yields:
I V2 - V1 = VT In REF (4) I PD Where IS1 and IS2 are saturation current V1, V2 are VBE, base-emitted voltages of the diode connector transistors VT is the thermal voltage, which is equal to k x T/q. VT = 26 mV at 25C k = Boltzmann's constant = 1.38E-23 Joules/Kelvin q = electron charge = 1.6E-19 coulomb T = temperature in Kelvin IPD = photodiode current IREF = reference current
The ADN2850 comes with a pair of matched diode connected PNPs, Q1 and Q2, that can be used to configure an incoming optical power monitoring function. With a reference current source, an instrumentation amplifier, and a logarithmic amplifier, this feature can be used to monitor the optical power by knowing the dc average photodiode current from the following relationships: I V1 = VBE1 = VT In C1 (2) I S1 I V2 = VBE2 = VT In C 2 (3) I S2
Figure 12 shows such a conceptual circuit.
POST AMP TIA 10nF LPF 0.75 BIT RATE DATA CDR CLOCK
IPD
IREF
VT COMPENSATION (1 + 100k/R G ) (V 2 - V 1) AD623 IN AMP LOG AVERAGE POWER
RG
ADN2850
W1 VDD Q1 Q2 W2 V1 V2 C PRC THERMISTOR
VSS
B1
B2
GND LOG AMP -5V
Figure 12. Conceptual Incoming Optical Power Monitoring Circuit
-16-
REV. B
ADN2850
The output voltage represents the average incoming optical power. The output voltage of the log stage does not have to be accurate from device to device, as the responsivity of the photodiode will change between devices. An op amp stage is shown after the log amp stage, which compensates for VT variation over temperature. Equation 4 is ideal. If the reference current is 1 mA at room temperature, characterization shows that there is an additional 30 mV offset between V2 and V1. A curve fit approximation yields
0.001 = 0.026 x In + 0.03 I PD
B1 W1 B2 W2
Figure 14. Reduce Resistance by Half with Linear Adjustment Characteristics
Much lower resistance can also be achieved by paralleling a discrete resistor as shown in Figure 15. (5)
W1 B1 R
V2
-- V1
Such offset is believed to be caused by the transistors self-heating and the thermal gradient effect. As seen in Figure 13, the error between an approximation and the actual performance ranges is less than 0% to -4% from 0.1 mA to 0.1 A.
0.30 DEVICE 1 DEVICE 2 DEVICE 3 CURVE FIT IREF = 1mA TA = 25 C 9 ERROR 6
APPROXIMATING ERROR - %
Figure 15. Resistor Scaling with Pseudo-Log Taper Adjustment Characteristics
12
The equivalent resistance at a given setting is approximated as: D x RWB_FS + 51200 D x RWB _ FS + 51200 + 1024 x R
0.25
0.20
V2 - V1 - V
Req =
(6)
0.15
3
0.10
0
In this approach, the adjustment is not linear but pseudologarithmic. Users should be aware of the need for tolerance matching as well as temperature coefficient matching of the components.
BASIC RDAC SPICE MODEL
RDAC 25k B CB = 11pF
0.05
-3
0 1.E-07
1.E-06
1.E-05 IPD - A
1.E-04
-6 1.E-03
Figure 13. Typical V2 - V1 vs. IPD at IREF = 1 mA and TA = 25C
Resistance Scaling
CW = 80pF
The ADN2850 offers either 25 k or 250 k full-scale resistance. Users who need lower resistance and still maintain the numbers of step adjustment can parallel two or more devices. Figure 14 shows a simple scheme of paralleling both channels of the programmable resistors. In order to adjust half of the resistance linearly per step, users need to program both devices coherently with the same settings. Note that since the devices will be programmed one after another, an intermediate state will occur, and this method may not be suitable for certain applications.
W
Figure 16. RDAC Circuit Simulation Model (RDAC = 25 k)
The internal parasitic capacitances and the external capacitive loads dominate the ac characteristics of the RADCs. A general parasitic simulation model is shown in Figure 16. Listing I provides a macro model net list for the 25 k RDAC: Listing I. Macro Model Net List for RDAC .PARAM D = 1024, RDAC = 25E3 * .SUBCKT RDAC (W, B) * RWB W B {D/1024 CW W 0 80E-12 CB B 0 11E-12 * .ENDS RDAC RDAC 50}
REV. B
-17-
ADN2850
OUTLINE DIMENSIONS 16-Lead Frame Chip Scale Package [LFCSP] 5 x 5 mm Body (CP-16 5x5)
Dimensions shown in millimeters
5.0 BSC SQ 0.60 MAX 0.60 MAX
13 12 16 1
PIN 1 INDICATOR
PIN 1 INDICATOR
0.80 BSC
TOP VIEW
4.75 BSC SQ 0.75 0.60 0.50
9 8
BOTTOM VIEW
4 5
3.25 3.10 2.95
12 MAX
0.70 MAX 0.65 NOM 0.05 MAX 0.01 NOM 0.40 0.33 0.28 0.20 REF COPLANARITY 0.08
2.40 BSC
0.90 MAX 0.85 NOM SEATING PLANE
COMPLIANT TO JEDEC STANDARDS MO-220VHHB
16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16)
Dimensions shown in millimeters
5.10 5.00 4.90
16
9
4.50 4.40 4.30
1 8
6.40 BSC
PIN 1 1.20 MAX 0.20 0.09 0.65 BSC 0.30 0.19 COPLANARITY 0.10 SEATING PLANE 8 0 0.75 0.60 0.45
0.15 0.05
COMPLIANT TO JEDEC STANDARDS MO-153AB
-18-
REV. B
ADN2850 Revision History
Location Page
9/02--Data sheet changed from REV. A to REV. B. Changes to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Changes to ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Changes to Calculating Actual Full-Scale Resistance section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Changes to Table VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
REV. B
-19-
-20-
C02660-0-9/02(B)
PRINTED IN U.S.A.

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